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S1C33401 seiko epson corporation cmos 32-bit single chip microcomputer the S1C33401 is a 32-bit risc-type microcomputer originally developed for embedded applications by seiko epson. the S1C33401 is built around the c33 adv core block that includes the cpu, mmu, cache, and modules that allow various external memory and i/o devices to be connected directly, and incorporates a bus block that includes the dma controller and other control units. in addition to these primary units, the S1C33401 incorporates a basic peripheral circuit block that includes an interrupt controller, timers, serial interfaces, card interfaces, input/output ports, and a/d converter, and an extended peripheral circuit block that includes a chip id register, rtc, and other components. the S1C33401 is manufactured by a 0.18 m fine-pattern cmos process, backed by sophisticated clock control functions, and can operate at higher speed with less power than ever before. in addition to its use as an embedded-type processor in various portable systems, the S1C33401 features a built-in c33 adv cpu to provide enhanced functionality for multimedia support while retaining upward compatibility with the conventional c33 std cpu, making it an ideal solution to the requirements of mobile multimedia applications. product lineup model no. package S1C33401f00a ??? qfp20-184pin S1C33401b00a ??? pfbga-160pin features core ? original seiko epson 32-bit risc-type cpu C c33 adv ? internal 32-bit data processing ? 4gb address space ? powerful instruction set - code length: 16 bits per instruction - number of instructions: 164 - main instructions executable in 1 cycle (including immediate-extended instructions, each consisting of two to three instructions) - 15.15 ns per instruction (when operating at 66 mhz, max.) ? multimedia support functions - built-in 32-bit 16-bit multiplier - 16 16, 32 16 and 32 32-bit multiplication - 16 16, 32 16 and 32 32-bit multiply-accumulate operations - repeated execution by loop and repeat instructions - rounding to minimum/maximum values by saturation instruction - alu instruction execution with post-shift high-speed bus control unit (hbcu) ? controls memory access by the cpu by dividing 4gb logical space into eight 512mb blocks. ? manages mmu, ccu, and asid processing in each block. ? capable of multiplexing logical space using asid and mirroring physical space. ? can simultaneously process a0ram data read/write operations and instruction fetching from cache.
S1C33401 2 epson memory ma nagement un it (mmu) co nv erts logical space into physical space in page units (4kb or 64kb per page). supports 16 entries per way for a total of 64 entries, due to 4-way set associative method. c an protect memory for each page. allows optional selection of using cache for each page. supports five causes of mmu exception. ca ch e co nt ro l un it (ccu) physical address-based instruction/data coexisting type of cache c ontains 8kb cache. supports 128 entries per way for a total of 512 lines, due to 4-way set associative method (4 words per line). allows selection of write-through or write-back mode for writing to cache. c an lock a specified way and interrupt handler routine. fo rwarding function to allow immediate instruction/data transfer even during refill. clo ck management unit (cmu) c ontrols reset and nmi input. s ystem clock control - selects clock source, turns clock on/o ff, and divides operating clock. - controls clock according to standby mode (sleep, halt, or halt2). c ontrols clock supply for each module (manual/auto). debu g unit (dbg) supports on-chip trace/break and other debugging functions at the chip level. provides an advanced debugging environment in conjunction with the icd (in-circuit debugger) and debugger. internal memory high-speed ram incorporated in area 0 (a0ram) 32kb hi gh-speed access with zero wait state ram incorporated in area 3 (a3ram) 1kb access wi th one wait state also usable as idma control information table bus co ntrol units and dma controller b asi c bu s c ont ro l un it (bbcu) c ontrols external address space by dividing it into 19 areas (areas 4 to 22). allows selection of external/internal access, endian mode, interface mode, device type, device size, and number of ac ce ss cyc le s fo r each area. outputs 8 chip-enable signals (#ce4?#ce11) corresponding to each external area. supports two interface modes: a0 and bsl (with bsl mode for external memory only). allows direct connection of sram, rom, burst rom, or flash memory to external bus. allows insertion of wait state from external #wait pin (for sram type only). arbitrates bus contention with external bus masters. exte nded bus control unit (ebcu) allows direct connection of sdram (in one of areas 4 to 22 selected). data bus widt h: 16 bits bank address: up to four banks accommodated. burst length: fixed to 1 (with burst read/write executed by issuing successive commands). c as latency: 1, 2, or 3 w rite mode: single write supports self-refresh and auto-refresh. programmable refresh cycle allows selection of bank active mode (with or without auto-precharge).
S1C33401 epson 3 high-speed dma controller (hsdma) ? up to four channels ? capable of high-speed dma transfer because of no need to read/write transfer conditions, etc. from/to memory. ? supports dual-address and single-address transfers. ? activated by dma request input, interrupt cause, or software trigger. ? can generate interrupt upon completion of transfer. intelligent dma controller (idma) ? up to 128 channels ? supports dual-address transfers. ? programmable dma transfer control information in ram (except a0ram) ? activated by a specific interrupt cause or software trigger. ? can be linked from one idma channel to another. ? can generate an interrupt upon completion of transfer. internal peripheral circuits ? generates the main system clock. ? crystal/ceramic oscillator: 5 mhz (min.) to 33 mhz (max.) ? external clock input: 2 mhz (min.) to 33 mhz (max.) pll ? allows selection of whether to use 1 to 16 osc3 oscillation frequency. ? pll input frequency: 5 mhz (min.) to 33 mhz (max.) ? pll output frequency: 20 mhz (min.) to 66 mhz (max.) sscg (spread spectrum clock generator) ? ss-modulation circuit for system source clock (osc3, pll, or osc1) to reduce electromagnetic interference (emi) noise interrupt controller (itc) ? branches to interrupt handling routine via interrupt vector table. ? can activate intelligent dma. ? handles 9 exceptions: - reset exception (1) - divide by zero exception (1) - address misaligned exception (1) - nmi (1) - software exceptions (4) - mmu exception (1) ? handles 64 maskable interrupts: - port/key input interrupts (18) - dma controller interrupts (5) - 16-bit timer interrupts (20) - 8-bit timer interrupts (6) - serial interface interrupts (12) - a/d converter interrupts (2) - rtc interrupt (1) prescaler (psc) ? programmable 8-bit and 16-bit timers, and a/d converter clock settings 8-bit timer (t8) ? 6-channel, 8-bit programmable timers ? can generate an interrupt upon underflow. ? can output the clock generated by underflow to external devices. ? generates serial interface clock as programmed. ? can output a trigger to a/d converter at specified intervals.
S1C33401 4 epson 16-bit timer (t16) ? 10-channel, 16-bit programmable timers ? can be used as pwm timer. ? supports da16 mode. ? can generate two interrupts per channel upon underflow or when matching compared value. ? can output clock generated by underflow or when matching compared value to external devices. watchdog timer (wdt) ? 30-bit watchdog timer capable of generating nmi ? programmable setting of nmi generation cycle serial interface (sio) ? 4 channels ? contains 4-byte receive data buffer (fifo) and 2-byte transmit data buffer (fifo) for each channel. ? supports full-duplex communication. ? selectable between 8-bit clock-synchronous and 8-bit or 7-bit asynchronous modes. ? supports irda 1.0 interface. ? can generate transmit buffer empty, receive buffer full, and receive error interrupts. card interface (card) ? supports smartmedia card (nand flash). ? supports compactflash card. ? supports pc card (2 channels). i/o ports (port) ? up to 71 ports ? can be used as general-purpose i/o pins when not used for peripheral functions. ? programmable port input and key input interrupts a/d converter (adc) ? 4-channel, 10-bit a/d converters ? can generate an interrupt upon completion of conversion. ? can generate an interrupt when converted value is outside specified upper and lower limits. rtc ? contains bcd time (second, minute, and hour) counters and calendar (day, days of the week, month, and year) counters. ? allows selection between 24-hour and 12-hour modes. ? equipped with function for 30-second correction in software. ? can periodically generate interrupts (at intervals of 1/64 or 1 second, 1 minute, or 1 hour). ? powered independently of other modules, and can operate even when system power is turned off. ? contains an osc1 oscillator circuit to generate 32.768 khz (typ.) clock. operating conditions and power consumption ? core power supply voltages (v dd , pllv dd , rtcv dd ): 1.65 v to 1.95 v (1.8 v 0.15 v) ? i/o power supply voltages (v dde , tmv dd , av dd ): 2.70 v to 3.60 v (3.0/3.3 v 0.3 v) input voltage ? high-level input voltage: 2.20 v (min.) to v dde (max.) ? low-level input voltage: v ss (min.) to 0.80 v (max.) operating clock frequency ? cpu: 66 mhz (max.) ? bus (bbcu, ebcu): 66 mhz (max.) operating temperature ? -40c to 85c
S1C33401 epson 5 power consumption ? in sleep mode: 25 w (typ.) ? in halt mode: 36 mw (typ., 66 mhz) ? during operation: 65 mw (typ., 66 mhz, cache off) form of shipment ? pfbga 160-pin plastic package (10 mm 10 mm 1.2 mm, 0.65 mm pitch) ? qfp20 184-pin plastic package (20 mm 20 mm 1.7 mm, 0.40 mm pitch) block diagram c33 adv cpu hbcu osc3/pll interrupt controller (itc) ccu mmu cmu dbg ebcu (sdram controller) dma a3ram (area 3 ram) bbcu (sram controller) bridge a0ram (area 0 no-wait ram) prescaler (psc) 8-bit timer (t8) 16-bit timer/pwm (t16) watchdog timer (wdt) serial interface (sio) card interface (card) i/o ports (port) a/d converter (adc) real time clock (rtc) chip id, pin control and misc. registers c33 adv core block S1C33401 bus control block standard peripheral block high-speed bus extended peripheral block (area 6) (area 1)
S1C33401 6 epson pin layout diagram qfp20-184pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 v ss #ce11 (p56) #ce9 (p55) #ce10 p27 (dqmh/#srdy3) p26 (dqml/#sclk3) v ss p21 (sdclk/sout2) v dd p25 (#sdwe/sout3) v dde p24 (#sdcas/sin3) p23 (#sdras/#srdy2) p22 (#sdcs/#sclk2) p20 (sdcke/sin2) v ss d15 d14 d13 v dde n.c. v dd n.c. d12 d11 v ss n.c. d10 d9 d8 d7 v dde d6 v ss d5 d4 d3 v dd d2 d1 v ss v dde d0 #bsl #wrh #wrl 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 p95 (sout3/astb/dtd5) p96 (#sclk3/card4/dtd6) p97 (#srdy3/card5/dtd7) v dde p82 (#dmaend2/excl5/dbt) p83 (#dmaend3/excl6/dts0) p84 (psc_clk/card2/dts1) p85 (cmu_clk/card3/dts2) v dd p86 (tm8/card0/dts3) p87 (tm9/card1/dts4) v ss p80 (#dmaack2/t8uf3/excl3) p81 (#dmaack3/t8uf4/excl4) v dde n.c. p30 (#dmareq0/t8uf0/excl0) p31 (#dmareq1/t8uf1/excl1) p32 (#dmareq2/card2/excl2) p33 (#dmareq3/card3/wdt_clk) p60 (#busreq/card4) p61 (#busack/card5) v ss n.c. v dd n.c. p62 (#busget/t8uf2/#adtrg) cmu_clk (p63/bclk/t8uf5) v dde #ce4 (p50/card0) #ce5 (p51) #ce6 (p52) #ce7 (p53/card1) #ce8 (p54) v ss p64 (#wait) tmv dd p10 (tm0) p11 (tm1) v dd p12 (tm2) p13 (tm3) p14 (tm4/#dmaend0) p15 (tm5/#dmaend1) p16 (tm6/#dmaack0) p17 (tm7/#dmaack1) 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 rtcv dd #stby osc1 osc2 pllv dd vcp pllv ss v dd burnin scanen osc3 osc4 v ss tst0 tst1 v dde #reset #nmi p00 (sin0) p01 (sout0) p02 (#sclk0) v dd n.c. p03 (#srdy0) p04 (sin1) n.c. v ss p05 (sout1) p06 (#sclk1) p07 (#srdy1) dsio dst0 (p65) dst1 (p66) dst2 v dd dpco (p67) v ss dclk v dde n.c. p90 (sin2/excl7/dtd0) p91 (sout2/excl8/dtd1) p92 (#sclk2/excl9/dtd2) p93 (#srdy2/r / w/dtd3) p94 (sin3/acst/dtd4) v ss 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 #rd v ss a0 a1 a2 v dde a3 a4 v ss a5 v dd a6 a7 a8 a9 a10 n.c. v dde n.c. v ss a11 v dd n.c. a12 a13 a14 a15 a16 a17 v ss a18 (p47) v dde a19 (p46) a20 (p45) a21 (p44) v dd a22 (p43) a23 (p42) a24 (p41) a25 (p40) v ss av dd p73 (ain3) p72 (ain2) p71 (ain1) p70 (ain0)
S1C33401 epson 7 pfbga-160pin top view bottom view a1 corner a1 corner index 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghj klmnp pnmlk jhgfedcba n.c. p95 sout3 astb dtd5 p97 #srdy3 card5 dtd7 p84 psc_clk card2 dts1 p86 tm8 card0 dts3 p81 #dmaack3 t8uf4 excl4 p32 #dmareq2 card2 excl2 cmu_clk p63 bclk t8uf5 #ce6 p52 p64 #wait p14 tm4 #dmaend0 p11 tm1 p70 ain0 n.c. a b c d e f g h j k l m n p a b c d e f g h j k l m n p 1 1 p92 #sclk2 excl9 dtd2 p93 #srdy2 r/w dtd3 p96 #sclk3 card4 dtd6 p83 #dmaend3 excl6 dts0 p30 #dmareq0 t8uf0 excl0 p61 #busack card5 p62 #busget t8uf2 #adtrg #ce5 p51 p12 tm2 p16 tm6 #dmaack0 p71 ain1 p72 ain2 2 p90 sin2 excl7 dtd0 p91 sout2 excl8 dtd1 p82 #dmaend2 excl5 dbt p85 cmu_clk card3 dts2 p87 tm9 card1 dts4 p31 #dmareq1 t8uf1 excl1 p60 #busreq card4 #ce7 p53 card1 p13 tm3 p17 tm7 #dmaack1 p73 ain3 3 dclk p67 dpco p94 sin3 acst dtd4 v dd p80 #dmaack2 t8uf3 excl3 p33 #dmareq3 card3 wdt_clk #ce4 p50 card0 #ce8 p54 p10 tm0 p15 tm5 #dmaend1 a25 p40 a24 p41 4 p66 dst1 p65 dst0 dsio dst2 v dd tmv dd a23 p42 a22 p43 a20 p45 5 p06 #sclk1 p05 sout1 p07 #srdy1 a21 p44 a19 p46 a18 p47 6 p03 #srdy0 v dd p04 sin1 p02 #sclk0 a16 a14 a17 a15 7 p00 sin0 #nmi p01 sout0 #reset a11 a13 a12 8 osc4 tst1 tst0 a6 a9 a8 a10 9 osc3 scanen burnin #ce11 p56 a4 a5 a7 10 v dd rtcv dd pllv dd vcp #ce9 p55 v dd p22 #sdcs #sclk2 d9 d3 #wrl a3 11 osc2 p26 dqml #sclk3 p25 #sdwe sout3 p23 #sdras #srdy2 d13 d11 d8 d4 v dd #wrh a1 a2 12 osc1 #stby #ce10 pllv ss p24 #sdcas sin3 d15 d14 d12 d10 d6 d2 #bsl a0 13 n.c. p27 dqmh #srdy3 p21 sdclk sout2 v dde v dde v dde av dd v dde v dde v dde v dde p20 sdcke sin2 v dd d7 d5 d1 d0 #rd n.c. 14 2345678 top view 9 1011121314 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss
S1C33401 8 epson pin description power supply pin list function power supply (+) for the internal logic circuits (1.65 v to 1.95 v) power supply (?; gnd power supply (+) for the pll (pllv dd = v dd ) power supply (? for the pll (pllv ss = v ss ) power supply (+) for the rtc (rtcv dd = v dd ) power supply (+) for the i/o block (2.7 v to 3.6 v) power supply (+) for pwm timer outputs (p1 x port) (tmv dd = v dde ) power supply (+) for the analog system and ain0?in3 (av dd = v dde ) qfp 9,25,40,57,71,82,101, 117,130,146,160,173 12,23,35,52,63,73,84,91,98, 105,113,123,132,138,151, 165,175,184 143 145 139 4,15,29,61,75,87,97,107, 119,128,154,177 37 51 pin no. pin name v dd v ss pllv dd pllv ss rtcv dd v dde tmv dd av dd pfbga b7,b11,e4,f11,g14, l5,l12 a11,b14,c3,d6,d13,e2, h14,k3,k11,l8,m10,n13 c12 d11 b12 d4,d9,e14,h4,h11,m6,n11 k2 n3 external bus pin list i/o i /o o o o o o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o i/ o pull-up ? 2 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 function data bus (d15?0) bus strobe (low byte) signal in bsl mode read signal write (low byte) signal in a0 mode or write signal in bsl mode write (high byte) signal in a0 mode or bus strobe (high byte) signal in bsl mode address bus (a17?0) a18: address bus (a18) (default) p47: general-purpose i/o port a19: address bus (a19) (default) p46: general-purpose i/o port a20: address bus (a20) (default) p45: general-purpose i/o port a21: address bus (a21) (default) p44: general-purpose i/o port a22: address bus (a22) (default) p43: general-purpose i/o port a23: address bus (a23) (default) p42: general-purpose i/o port a24: address bus (a24) (default) p41: general-purpose i/o port a25: address bus (a25) (default) p40: general-purpose i/o port #ce11: chip enable signal for areas 11 and 12 (default) p56: general-purpose i/o port chip enable signal for areas 10, 13 and 20 #ce9: chip enable signal for areas 9 and 22 (default) p55: general-purpose i/o port #ce8: chip enable signal for areas 8 and 21 (default) p54: general-purpose i/o port qfp 122?20, 115,114, 111?08, 106, 104?02, 100,99, 96 95 92 93 94 64?9, 72, 77?1, 83,85, 86, 88?0 62 60 59 58 56 55 54 53 137 135 136 34 pin no. pin name d[15:0] #bsl #rd #wrl #wrh a[17:0] a18 p47 a19 p46 a20 p45 a21 p44 a22 p43 a23 p42 a24 p41 a25 p40 #ce11 p56 #ce10 #ce9 p55 #ce8 p54 pfbga f13,g13, g12,h13, h12,j13, j11,j12, j14,k13, k14,k12, l11,l13, l14,m14 m13 n14 m11 m12 n7,l7, p7,m7, n8,p8, m8,p9, m9,n9, p10,l9, n10,l10, p11,p12, n12,p13 p6 n6 p5 l6 n5 m5 p4 n4 d10 c13 e11 k4 module bbcu ebcu bbcu bbcu bbcu bbcu bbcu ebcu bbcu port bbcu port bbcu port bbcu port bbcu port bbcu port bbcu port bbcu port bbcu port bbcu bbcu port bbcu port
S1C33401 epson 9 i/o i/ o i/ o i/ o i/ o pull-up ? 1 ? 1 ? 1 ? 1 function #ce7: chip enable signal for areas 7 and 19 (default) p53: general-purpose i/o port card1:card i/f signal 1 output (#smwr or #cfce2) #ce6: chip enable signal for areas 6, 17 and 18 (default) p52: general-purpose i/o port #ce5: chip enable signal for areas 5, 15 and 16 (default) p51: general-purpose i/o port #ce4: chip enable signal for areas 4 and 14 (default) p50: general-purpose i/o port card0:card i/f signal 0 output (#smrd or #cfce1) qfp 33 32 31 30 pin no. pin name #ce7 p53 card1 #ce6 p52 #ce5 p51 #ce4 p50 card0 pfbga j3 j1 j2 j4 module bbcu port card bbcu port bbcu port bbcu port card input/output port and peripheral circuit pin list i/o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o pull-up ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 function p00: general-purpose i/o port (default) sin0: serial i/f ch.0 data input p01: general-purpose i/o port (default) sout0: serial i/f ch.0 data output p02: general-purpose i/o port (default) #sclk0: serial i/f ch.0 clock input/output p03: general-purpose i/o port (default) #srdy0: serial i/f ch.0 ready signal input/output p04: general-purpose i/o port (default) sin1: serial i/f ch.1 data input p05: general-purpose i/o port (default) sout1: serial i/f ch.1 data output p06: general-purpose i/o port (default) #sclk1: serial i/f ch.1 clock input/output p07: general-purpose i/o port (default) #srdy1: serial i/f ch.1 ready signal input/output p10: general-purpose i/o port (default) tm0: 16-bit timer 0 output p11: general-purpose i/o port (default) tm1: 16-bit timer 1 output p12: general-purpose i/o port (default) tm2: 16-bit timer 2 output p13: general-purpose i/o port (default) tm3: 16-bit timer 3 output p14: general-purpose i/o port (default) tm4: 16-bit timer 4 output #dmaend0: hsdma ch.0 end-of-transfer signal output p15: general-purpose i/o port (default) tm5: 16-bit timer 5 output #dmaend1: hsdma ch.1 end-of-transfer signal output p16: general-purpose i/o port (default) tm6: 16-bit timer 6 output #dmaack0: hsdma ch.0 acknowledge signal output p17: general-purpose i/o port (default) tm7: 16-bit timer 7 output #dmaack1: hsdma ch.1 acknowledge signal output p20: general-purpose i/o port (default) sdcke: sdram clock enable signal output sin2: serial i/f ch.2 data input p21: general-purpose i/o port (default) sdclk: sdram clock output sout2: serial i/f ch.2 data output p22: general-purpose i/o port (default) #sdcs: sdram chip enable signal output #sclk2: serial i/f ch.2 clock input/output p23: general-purpose i/o port (default) #sdras: sdram row address strobe signal output #srdy2: serial i/f ch.2 ready signal input/output p24: general-purpose i/o port (default) #sdcas: sdram column address strobe signal output sin3: serial i/f ch.3 data input qfp 157 158 159 162 163 166 167 168 38 39 41 42 43 44 45 46 124 131 125 126 127 pin no. pin name p00 sin0 p01 sout0 p02 #sclk0 p03 #srdy0 p04 sin1 p05 sout1 p06 #sclk1 p07 #srdy1 p10 tm0 p11 tm1 p12 tm2 p13 tm3 p14 tm4 #dmaend0 p15 tm5 #dmaend1 p16 tm6 #dmaack0 p17 tm7 #dmaack1 p20 sdcke sin2 p21 sdclk sout2 p22 #sdcs #sclk2 p23 #sdras #srdy2 p24 #sdcas sin3 pfbga a8 c8 d7 a7 c7 b6 a6 c6 l4 l1 l2 l3 m1 m4 m2 m3 f14 d14 g11 f12 e13 module port sio port sio port sio port sio port sio port sio port sio port sio port t16 port t16 port t16 port t16 port t16 hsdma port t16 hsdma port t16 hsdma port t16 hsdma port ebcu sio port ebcu sio port ebcu sio port ebcu sio port ebcu sio
S1C33401 10 epson i/o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i i i i i /o i /o i /o i /o i /o pull-up ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 function p25: general-purpose i/o port (default) #sdwe: sdram write signal output sout3: serial i/f ch.3 data output p26: general-purpose i/o port (default) dqml: sdram data (low byte) input/output mask signal output #sclk3: serial i/f ch.3 clock input/output p27: general-purpose i/o port (default) dqmh: sdram data (high byte) input/output mask signal output #srdy3: serial i/f ch.3 ready signal input/output p30: general-purpose i/o port (default) #dmareq0:hsdma ch.0 request input t8uf0: 8-bit timer 0 output excl0: 16-bit timer 0 event counter input p31: general-purpose i/o port (default) #dmareq1:hsdma ch.1 request input t8uf1: 8-bit timer 1 output excl1: 16-bit timer 1 event counter input p32: general-purpose i/o port (default) #dmareq2:hsdma ch.2 request input card2: card i/f signal 2 output (#iord or #smrd) excl2: 16-bit timer 2 event counter input p33: general-purpose i/o port (default) #dmareq3:hsdma ch.3 request input card3: card i/f signal 3 output (#iowr or #smwr) wdt_clk: watchdog timer output p60: general-purpose i/o port (default) #busreq: bus release request input card4: card i/f signal 4 output (#oe or #cfce1) p61: general-purpose i/o port (default) #busack: bus acknowledge output card5: card i/f signal 5 output (#we or #cfce2) p62: general-purpose i/o port (default) #busget: bus status monitor signal output t8uf2: 8-bit timer 2 output #adtrg: a/d converter trigger input p64: general-purpose i/o port (default) #wait: wait cycle request input p70: general-purpose i/o port (default) ain0: a/d converter ch.0 input p71: general-purpose i/o port (default) ain1: a/d converter ch.1 input p72: general-purpose i/o port (default) ain2: a/d converter ch.2 input p73: general-purpose i/o port (default) ain3: a/d converter ch.3 input p80: general-purpose i/o port (default) #dmaack2: hsdma ch.2 acknowledge signal output t8uf3: 8-bit timer 3 output excl3: 16-bit timer 3 event counter input p81: general-purpose i/o port (default) #dmaack3: hsdma ch.3 acknowledge signal output t8uf4: 8-bit timer 4 output excl4: 16-bit timer 4 event counter input p82: general-purpose i/o port (default) #dmaend2: hsdma ch.2 end-of-transfer signal output excl5: 16-bit timer 5 event counter input dbt: dbt signal output for debugging p83: general-purpose i/o port (default) #dmaend3: hsdma ch.3 end-of-transfer signal output excl6: 16-bit timer 6 event counter input dts0: dts0 signal output for debugging p84: general-purpose i/o port (default) psc_clk: prescaler clock output card2: card i/f signal 2 output (#iord or #smrd) dts1: dts1 signal output for debugging qfp 129 133 134 17 18 19 20 21 22 27 36 47 48 49 50 13 14 5 6 7 pin no. pin name p25 #sdwe sout3 p26 dqml #sclk3 p27 dqmh #srdy3 p30 #dmareq0 t8uf0 excl0 p31 #dmareq1 t8uf1 excl1 p32 #dmareq2 card2 excl2 p33 #dmareq3 card3 wdt_clk p60 #busreq card4 p61 #busack card5 p62 #busget t8uf2 #adtrg p64 #wait p70 ain0 p71 ain1 p72 ain2 p73 ain3 p80 #dmaack2 t8uf3 excl3 p81 #dmaack3 t8uf4 excl4 p82 #dmaend2 excl5 dbt p83 #dmaend3 excl6 dts0 p84 psc_clk card2 dts1 pfbga e12 d12 c14 f2 g3 g1 g4 h3 g2 h2 k1 n1 n2 p2 p3 f4 f1 d3 d2 d1 module port ebcu sio port ebcu sio port ebcu sio port hsdma t8 t16 port hsdma t8 t16 port hsdma card t16 port hsdma card wdt port bbcu card port bbcu card port bbcu t8 adc port bbcu port adc port adc port adc port adc port hsdma t8 t16 port hsdma t8 t16 port hsdma t16 dbg port hsdma t16 dbg port psc card dbg
S1C33401 epson 11 i/o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o i /o pull-up ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 function p85: general-purpose i/o port (default) cmu_clk: cmu external clock output card3: card i/f signal 3 output (#iowr or #smwr) dts2: dts2 signal output for debugging p86: general-purpose i/o port (default) tm8: 16-bit timer 8 output card0: card i/f signal 0 output (#smrd or #cfce1) dts3: dts3 signal output for debugging p87: general-purpose i/o port (default) tm9: 16-bit timer 9 output card1: card i/f signal 1 output (#smwr or #cfce2) dts4: dts4 signal output for debugging p90: general-purpose i/o port (default) sin2: serial i/f ch.2 data input excl7: 16-bit timer 7 event counter input dtd0: dtd0 signal output for debugging p91: general-purpose i/o port (default) sout2: serial i/f ch.2 data output excl8: 16-bit timer 8 event counter input dtd1: dtd1 signal output for debugging p92: general-purpose i/o port (default) #sclk2: serial i/f ch.2 clock input/output excl9: 16-bit timer 9 event counter input dtd2: dtd2 signal output for debugging p93: general-purpose i/o port (default) #srdy2: serial i/f ch.2 ready signal input/output r/w: read/write status output dtd3: dtd3 signal output for debugging p94: general-purpose i/o port (default) sin3: serial i/f ch.3 data input acst: bus access status output dtd4: dtd4 signal output for debugging p95: general-purpose i/o port (default) sout3: serial i/f ch.3 data output astb: address strobe output dtd5: dtd5 signal output for debugging p96: general-purpose i/o port (default) #sclk3: serial i/f ch.3 clock input/output card4: card i/f signal 4 output (#oe or #cfce1) dtd6: dtd6 signal output for debugging p97: general-purpose i/o port (default) #srdy3: serial i/f ch.3 ready signal input/output card5: card i/f signal 5 output (#we or #cfce2) dtd7: dtd7 signal output for debugging qfp 8 10 11 179 180 181 182 183 1 2 3 pin no. pin name p85 cmu_clk card3 dts2 p86 tm8 card0 dts3 p87 tm9 card1 dts4 p90 sin2 excl7 dtd0 p91 sout2 excl8 dtd1 p92 #sclk2 excl9 dtd2 p93 #srdy2 r/w dtd3 p94 sin3 acst dtd4 p95 sout3 astb dtd5 p96 #sclk3 card4 dtd6 p97 #srdy3 card5 dtd7 pfbga e3 e1 f3 a3 b3 a2 b2 c4 b1 c2 c1 module port cmu card dbg port t16 card dbg port t16 card dbg port sio t16 dbg port sio t16 dbg port sio t16 dbg port sio bbcu dbg port sio bbcu dbg port sio bbcu dbg port sio card dbg port sio card dbg debug pin list i/o i /o o (h) o (l) i/ o (h) i/ o (h) i/ o (h) pull-up pull-up ? 1 ? 1 ? 1 function serial input/output for debugging dclk signal output for debugging dst2 signal output for debugging dst0: dst0 signal output for debugging (default) p65: general-purpose i/o port dst1: dst1 signal output for debugging (default) p66: general-purpose i/o port dpco: dpco signal output for debugging (default) p67: general-purpose i/o port qfp 169 176 172 170 171 174 pin no. pin name dsio dclk dst2 dst0 p65 dst1 p66 dpco p67 pfbga c5 a4 d5 b5 a5 b4 module dbg dbg dbg dbg port dbg port dbg port
S1C33401 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arisi ng out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject rela ting to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government agency. ? seiko epson corporation 2007, all right reserved. seiko epson corporation epson electronic devices website semiconductor operations div ision ic sales dept. ic international sales group document code: 410036601 421-8, hino, hino-shi, tokyo 191-8501, japan issue june, 2007 phone: +81-42-587-5814 fax: +81-42-587-5117 printed in japan other pin list i/o i o i o o i/ o i i i i i i i pull- up/down ? 1 pull-up pull-up pull-down pull-down pull-down function low speed (osc1) oscillator input (32 khz crystal or external clock input with v dd level) low speed (osc1) oscillator output high speed (osc3) oscillator input (crystal/ceramic or external clock input with v dd level) high speed (osc3) oscillator output pll analog monitor (used for current monitor) cmu_clk: cmu external clock output (default) p63: general-purpose i/o port bclk: bus clock output t8uf5: 8-bit timer 5 output initial reset input pin nmi request input pin test input pin 0 (connect to v ss during normal operation) test input pin 1 (connect to v ss during normal operation) wafer level burn-in test enable input scan test enable input standby input for disabling c33 operation (except rtc) qfp 141 142 149 150 144 28 155 156 152 153 147 148 140 pin no. pin name osc1 osc2 osc3 osc4 vcp cmu_clk p63 bclk t8uf5 #reset #nmi tst0 tst1 burnin scanen #stby pfbga a13 a12 a10 a9 c11 h1 d8 b8 c9 b9 c10 b10 b13 module osc osc osc osc cmu cmu port bbcu t8 cmu cmu rtc ? 1: these pins can have pull-ups enabled or disabled by setting the pin control registers. (pull-ups are enabled by default.) ? 2: these pins come with a bus hold latch. notes : ? the # prefixed to pin names indicates that input/output signals of the pin are active low. ? the pin names and i/o printed in boldface denote the default pin (signal) name and default input/output direction. ? (h) and (l) for i/o indicate the default output level. this is only indicated for signals whose level is fixed high or low w hen the chip is initially reset. ? the input level must be v dd only for the osc1 and osc3 pins. input levels for other pins should be v dde (av dd , tmv dd ) level.

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